1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and a process for fabricating the same. The thin film transistor fabricated according to the present invention can be formed on either an insulator substrate such as a glass substrate or a substrate made of, for example, a crystalline silicon. In particular, the present invention relates to a thin film transistor fabricated through steps of crystallization and activation by thermal annealing.
2. Prior Art
Recently, active study is made on semiconductor devices of insulated-gate type comprising an insulator substrate having thereon a thin film active layer (which is sometimes referred to as xe2x80x9cactive regionxe2x80x9d). In particular, much effort is paid on the study of insulated-gate transistors of thin film type, i.e., the so-called thin film transistors (TFTs). The TFTs are formed on a transparent insulator substrate, so that they can be employed mainly for controlling each of the pixels or driver circuits of matrix-driven display devices. The TFTs can be classified into, for example, amorphous silicon TFTs and crystalline silicon TFTs, according to the material and the state of the semiconductor employed in the TFT.
Among the TFTs enumerated above, amorphous TFTs can be fabricated without involving a high temperature process. The amorphous TFTs are already put into practice because they yield a high product yield when fabricated on a large area substrate. In general, reverse staggered type (which is also referred to as bottom gate type) amorphous silicon TFTs are used in the practical amorphous silicon TFTs. The amorphous silicon TFTs of this type comprises a gate electrode under the active region.
The process for fabricating the present day TFTs comprises the steps of: forming a gate electrode on a substrate; forming an amorphous silicon film as a gate insulating film and an active layer; and forming an N-type fine-crystalline silicon film on the amorphous silicon film to provide source and drain regions. However, since the N-type silicon film and the amorphous silicon film provided as a base are etched at almost the same etching rate, this process requires an additional step of, for example, providing an etching stopper and the like.
As a means to overcome the above problems, there is proposed a method of forming source and drain by directly implanting high speed ions into the amorphous silicon film using an ion doping process.
However, this method is not yet satisfactory in that it yields. ion-implanted regions having particularly impaired crystallinity. These regions yield low electric conductivity and are therefore not suitable for use as they are. There is proposed to increase the crystallinity of these regions by annealing using optical energy from laser beams and the like, however, the method is not applicable to mass production.
Practically useful method at present is crystallizing the amorphous silicon by heating. This method, however, requires annealing at a temperature of 600xc2x0 C. or higher. Accordingly, this process also is not favorable in view of the problem of substrates. More specifically, an alkali-free glass substrate generally used in amorphous silicon TFTs initiates deformation at a temperature of 600xc2x0 C. or lower (e.g., a Corning #7059 glass substrate softens at 593xc2x0 C.). An annealing at 600xc2x0 C. causes a glass substrate to undergo shrinkage or warping.
Furthermore, an annealing at 600xc2x0 C. impairs the characteristics of an amorphous silicon TFT which can be advantageously fabricated at low temperatures. More specifically, the active regions also undergo crystallization at 600xc2x0 C. to completely lose the advantageous characteristics; i.e., the amorphous silicon TFT no longer is characterized by its low leak current. This problem demands the crystallization process to be conducted at a lower temperature (preferably, at a temperature lower than the deformation temperature of glass by 50xc2x0 C. or more).
In general, semiconductors in an amorphous state have a low electric field mobility. Accordingly, they cannot be used in TFTs in which high speed operation is required. Furthermore, the electric field mobility of a P-type amorphous silicon is extremely low. This makes the fabrication of a P-channel TFT (a PMOS TFT) unfeasible. It then follows that a complementary MOS circuit (CMOS) is not obtainable, because a P-channel TFT must be combined with an N-channel (NMOS TFT) for the implementation of a CMOS.
In contrast to the amorphous semiconductors, crystalline semiconductors have higher electric field mobilities, and are therefore suitable for use in the high speed operation of TFTs. Crystalline silicon is further advantageous in that a CMOS circuit can be easily fabricated therefrom, because not only an NMOS TFT but also a PMOS TFT is available from crystalline silicon. Accordingly, there is proposed an active-matrix driven liquid crystal display having a so-called monolithic structure comprising crystalline TFTs in CMOS, not only in the active matrix portion but also in the peripheral circuit (such as the driver circuit) thereof. These reasons have made the research and development of TFTs using crystalline silicon more active these days.
A crystalline silicon can be obtained from an amorphous silicon by irradiating a laser beam or an intense light having an intensity equivalent thereto. However, this process is not suitable for mass production; it is still unstable because the laser output itself lacks stability and because the process is too short.
A possible practical process for crystallizing amorphous silicon at present is applying heat treatment, i.e., thermal crystallization. This process allows the production of crystalline silicon with uniform quality irrespective of the batches. The process, still, have problems yet to be solved.
In general, thermal crystallization requires performing annealing at about 600xc2x0 C. for a long duration of time, or at a temperature as high as 1,000xc2x0 C. or even higher. The latter process narrows the selection of substrate material, because it cannot be applied to cases in which substrates other than those made of quartz are used, and the former treatment also suffer other problems.
More specifically, a process for fabricating a TFT using an inexpensive alkali-free glass substrate (such as a Corning #7059 glass substrate) comprises:
depositing an amorphous silicon film on the substrate;
crystallizing the amorphous silicon film at 600xc2x0 C. or higher for a duration of 24 hours or longer;
depositing a gate insulating film;
forming a gate electrode;
introducing impurities (by ion implantation or ion doping);
activating the doped impurities at 600xc2x0 C. or higher and for a duration of 24 hours or longer;
forming interlayer insulators; and
forming source and drain regions.
Among the process steps above, the sixth step of activating the doped impurities is found most problematic. Most of alkali-free glasses undergo deformation at the vicinity of 600xc2x0 C. (e.g., the deformation temperature of Corning #7059 glass is 593xc2x0 C.). This signifies that the shrinkage of the substrate must be taken into account in this step. In the second step, i.e., the step of annealing, the shrinkage of the substrate is of no problem because the substrate is not patterned yet. However, the substrate in the sixth step has thereon a patterned circuit, and, if the substrate undergoes shrinkage, the mask fitting in the later steps cannot be performed. This considerably lowers the product yield. Conclusively, it has been demanded to perform the sixth step a lower temperature, preferably, at a temperature lower than the glass deformation temperature by 50xc2x0 C. or more.
The process temperature can be lowered by using laser, as mentioned hereinbefore. However, the process has poor reliability, because of, not only the instability of the laser, but also the generation of stress, ascribed to the difference in temperature rise between the portion to which the laser is irradiated (the source and drain regions) and the portion to which the laser is not irradiated (the active region; i.e., the region under the gate electrode).
It has been therefore believed that the application of laser to the fabrication of TFTs is difficult. Still, no other effective means to overcome the problems could be found to present. The present invention provides a solution to the aforementioned difficulties. That is, the present invention aims to provide a process which overcomes the problems above and yet suitable for mass production.
As a result of an extensive study of the present inventors, it has been found that the crystallization of a substantially amorphous silicon film can be accelerated by adding a trace amount of a catalyst material. In this manner, the crystallization can be effected at a lower temperature and in a shorter duration of time. Preferred catalyst materials include pure metals, i.e., nickel (Ni), iron (Fe), cobalt (Co), and platinum (Pt), or a compound such as a silicide of an element enumerated herein. More specifically, the process according to the present invention comprises forming, over or under an amorphous silicon film and also in contact therewith, a material containing the catalyst elements in the form of a film, particles, clusters, etc., and thermally annealing the thus formed material for crystallization at a proper temperature, typically at 580xc2x0 C. or lower, and preferably at 550xc2x0 C. or lower. Otherwise, instead of forming the material containing the catalyst element in contact with the amorphous silicon film, the catalyst element may be incorporated into the amorphous silicon film by a means such as ion implantation.
Naturally, the duration of crystallization can be shortened by increasing the annealing temperature. Furthermore, the duration of crystallization becomes shorter and the crystallization temperature becomes lower with increasing concentration of nickel, iron, cobalt, or platinum. The present inventors have found, through an extensive study, that the crystallization is accelerated by incorporating at least one of the catalytic elements above at a concentration higher than 1xc3x971017 cmxe2x88x923, and preferably, at a concentration of 5xc3x971018 cmxe2x88x923 or higher.
The catalyst materials enumerated above, however, are not favorable for silicon. Accordingly, the concentration thereof are preferably controlled to a level as low as possible. The present inventors have found through the study that the preferred range of the concentration in total is 1xc3x971020 cmxe2x88x923 or lower. Particularly, in an active layer, the concentration of the catalyst materials must be controlled to 1xc3x971018 cmxe2x88x923 or lower, preferably, less than 1xc3x971017 cmxe2x88x923, and more preferably, less than 1xc3x971016 cmxe2x88x923.